The present invention relates to multi-phase sampling. In particular, the present invention provides a multi-phase sampling system that overcomes problems with current multi-phase systems that result from the inability of these multi-phase sampling systems to optimally sample an incoming data signal.
An ever-increasing demand exists for communications systems that are capable of operating at increasingly higher data rates. As monolithic processes (e.g., complementary metal oxide semiconductor (CMOS)) are increasingly being used to create devices that perform high-speed data processing, it has become necessary to use multiple phases in the devices for sampling and processing incoming signals in order to sample the incoming data signals at the Nyquist rate. The need for using multiple samplers in order to sample the data signal at a high enough speed can be seen from the following example. The cycle or retrigger time of a data retiming latch is often limited by the regeneration speed of the internal positive feedback circuitry of the latch. Although such a sampler or latch cannot be retriggered fast enough to Nyquist sample an incoming signal of a particularly high data rate, it is capable of taking a snapshot of a rapidly changing signal. By using a multiplicity of samplers on evenly staggered clock phases, each latch can be allowed a generous regeneration time, while still enabling sampling of the data signal at the Nyquist rate. An example of a known multi-phase system is a 3.5 gigabit per second (Gb/s) retiming circuit for non-return-to-zero (NRZ) data that uses a 10-phase sampling system built in 0.28 micrometer (um) CMOS. Such a system is disclosed in ISSCC Digest of Technical Papers, Vol. 42, pages 352–353 and 478, Feb. 15–17, 1999.
These and similar types of systems share the strategy of processing high-speed incoming signals by using multiple lower-speed samplers that all sample the incoming signal in a round-robin fashion. The samplers are lower in speed because they are comprised of larger transistors, which have larger parasitic capacitances, and thus have longer regeneration times and slower retrigger times. Due to the slower speeds of the large samplers, many samplers may be required in order to sample a very high data rate signal at the Nyquist rate. Also, because the samplers are larger in size, they dissipate more power. Obviously, such systems have many disadvantages that need to be overcome.
Multi-phase systems are also used to transmit data. In these systems, data is transmitted by using multiple phases to control respective selectors, each of which gates a different bit to the output of the transmitting multi-phase system. In this case, the jitter of each data edge is determined by the timing error of each data phase.
For monolithic implementations (e.g., CMOS), it is common to generate the multiple phases using a ring oscillator. The most common form of ring oscillator utilizes a number N of identical gain stages, each with a delay of τ, connected in a ring with a net inversion. As is well known in the art, such a system oscillates with a period of 2Nτ, and produces 2N evenly-spaced timing phases, with the phases being derived from both the rising and falling edges of each delay cell output. Such oscillators can be made tunable and are well-suited for monolithic IC implementation. However, such systems are designed such that the number of phases is even, i.e., for 2N evenly-spaced phases, where N is an integer.
In practice, the exact delay of oscillator elements will differ between the N different cells. These variations include random cycle-to-cycle delay variations, resulting largely from thermal, supply, and substrate noise in the devices, and deterministic delay errors, which are consistent cycle after cycle. These static delay errors can be caused by a number of factors, including: 1) device size variation due to fabrication errors that occur during the IC fabrication process, 2) non-symmetrical layout of the various delay cells, including capacitance, resistance and inductive mismatches caused by unequal wiring or crosstalk with other signals, 3) unequal proximity of various delay cells to other features which causes variations in doping or dielectric thickness to occur and/or unequal loading of the various delay outputs which can cause mismatched fan-out delays.
In addition, these same delay variations can afflict the clock distribution network. Because of its distributed nature, the clock network may also suffer from delay mismatches due to unequal supply voltages caused by resistive drops across the power distribution network. Also, it is possible for variations in the clock-to-sample delay between the input samplers to occur. The sum of all these errors results in an overall phase sampling error in the system.
One known way of preventing or reducing these phase errors is to decrease the aforementioned error factors 1)–3). However, solutions for doing this are difficult to implement and, thus far, have not been totally satisfactory. Furthermore, implementing these solutions typically result in increases in power dissipation and circuit size, and/or place an onerous burden on the designer to create precisely symmetrical samplers. Furthermore, such solutions must be implemented during device design and fabrication, not after the device has already been created. Therefore, failure to satisfactorily implement the solutions during the design and manufacturing process will likely result in phase error sampling problems occurring during operation of the device.
Another approach that has been used to eliminate phase error sampling problems in multi-phase systems is to focus on ensuring that the clock is very precise and to use very large samplers (referred to herein interchangeably as “latches”). If relatively small latches are used with a very precise clock, sampling errors will still occur due to the fact that the parasitic capacitances of the smaller transistors of the smaller latches result in very significant timing mismatches between the latches. However, if very large latches are used, which means that very large transistors are used to create the latches, the latches are slower and the timing mismatches caused by the differences in the parasitic capacitances of the transistors of the latches are less significant. Therefore, using very large latches with a very precise clock can decrease or eliminate sampling problems caused by phase errors, but there is a tradeoff. As stated above, larger latches take up more area, are slower than smaller latches and also consume more power than smaller latches, which are all undesirable traits in circuit design.
Accordingly, a need exists for a multi-phase system that is capable of sampling high speed signals at the Nyquist rate and that does not require the use of large samplers, which normally have relatively high power consumption requirements. A need also exists for a multi-phase system that does not require that the clock be precise or that the layout for each sampler be completely symmetrical, thus eliminating onerous burdens that would otherwise be placed on designers and manufacturers to create perfectly symmetrical latches and/or perfectly precise clocks.